(1) Field of the Invention
This invention relates to a semiconductor device fabrication method, a semiconductor device, and a semiconductor layer formation method and, more particularly, to a method for fabricating a semiconductor device having a semiconductor layer formed by epitaxial growth, such a semiconductor device, and a method for forming a semiconductor layer by the epitaxial growth.
(2) Description of the Related Art
In recent years attention has been riveted on what is called a recessed source/drain MOS field-effect transistor (MOSFET) in which a semiconductor layer that differs from a semiconductor substrate in lattice constant is formed in recesses formed in the semiconductor substrate as source/drain regions. Such a recessed source/drain MOSFET has become important as a technique for improving the performance of transistors beyond the 90 nm node.
If a silicon (Si) substrate is used in a recessed source/drain MOSFET as a semiconductor substrate, a silicon germanium (SiGe) layer or a silicon carbide (SiC) layer is used in many cases as source/drain regions according to the channel type of the MOSFET. If a SiGe layer, for example, is used as source/drain regions, compression distortion is caused in a channel region between the source/drain regions because the lattice constant of SiGe is greater than the lattice constant of Si. This improves hole mobility in the channel region. Therefore, the current driving capability of a p-channel MOSFET (pMOSFET) can be enhanced significantly.
Such a SiGe layer, for example, is formed by performing selective epitaxial growth in recesses formed in a Si substrate. In this case, the formation of the SiGe layer over insulating layers, such as shallow trench isolations (STIs) and a side wall, is suppressed. Conventionally, a chemical vapor deposition (CVD) method has widely been used for making such a SiGe layer, for example, selectively grow. In this case, a method in which Si material gas, germanium (Ge) material gas, and the like and halogen gas, such as hydrogen chloride (HCl) gas, are added is proposed.
The higher temperature at which a SiGe layer or the like grows becomes, the thinner the critical thickness of the SiGe layer gets. As a result, a misfit dislocation tends to appear in the SiGe layer. When a misfit dislocation appears, the distortion mitigates and stress applied to the channel region weakens. In addition, growth at a high temperature causes the diffusion of impurities contained in the semiconductor substrate. This has a bad influence on device characteristics. For example, a roll-off characteristic deteriorates. As transistors grow minuter and channels become shorter, such a bad influence on device characteristics becomes significant. To avoid these problems, a low-temperature process in which a SiGe layer is made to grow at a lower temperature is required.
For example, one possible method for making a SiGe layer of a MOSFET grow by the CVD method is as follows. When a SiGe layer is made to grow over a Si layer which is exposed with insulating layers such as a side wall and STIs or insulating layers for masking, halogen gas is added to Si material gas and Ge material gas. In this case, an increase in the content of halogen gas improves the growth selectivity of the SiGe layer over the Si layer with respect to the insulating layers. However, if the content of halogen gas is increased, that is to say, if the condition that the growth selectivity of the SiGe layer over the Si layer becomes higher is used, morphology deteriorates. For example, a partial delay in the growth of the SiGe layer occurs. This morphological deterioration largely depends on temperature at which the SiGe layer grows, and tends to occur when the SiGe layer grows at a low temperature. Such morphological deterioration has a great influence on the electrical characteristics of the MOSFET and, more particularly, on variation in the electrical characteristics of the MOSFET.
As stated above, when the SiGe layer is made to grow by adding halogen gas, there is a trade-off relationship between growth selectivity and morphology. The same applies to the case where a SiC layer, for example, is made to grow. Therefore, a technique for enabling the selective growth of a semiconductor layer, such as a SiGe layer or a SiC layer, and suppression of morphological deterioration at a low temperature and for stably fabricating a recessed source/drain MOSFET having excellent characteristics is desperately needed.